1. Field
Example embodiments relate to semiconductor memory devices, and more particularly, to semiconductor memory devices having hierarchical bit-line structures.
2. Description of Related Art
Conventional semiconductor memory devices read data from their own memory cells and store data in the memory cells via bit lines connected to the memory cells. But, integration density of conventional semiconductor memory devices is gradually increasing. Accordingly, the number of memory cells per unit area and the number of memory cells connected by one or a pair of bit lines is also increasing. Such an increase in the number of memory cells connected to each bit line inevitably causes parasitic capacitance to increase and degrades an operating speed of the semiconductor memory device.
A hierarchical bit-line structure has been proposed to reduce parasitic capacitance of bit lines and reduce chip size even with increasing integration density. However, a conventional semiconductor memory device having a hierarchical bit-line structure suffers from noise caused by coupling capacitance between adjacent global bit lines.